24C08B/16B
5.0
ACKNOWLEDGE POLLING
7.0
READ OPERATION
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the stop condition for a write com-
mand has been issued from the master, the device ini-
Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the
slave address is set to one. There are three basic
types of read operations: current address read, ran-
dom read, and sequential read.
tiates the internally timed write cycle. ACK polling can
be initiated immediately. This involves the master send-
7.1
Current Address Read
ing a start condition followed by the control byte for a
write command (R/W = 0). If the device is still busy with
the write cycle, then no ACK will be returned. If the
cycle is complete, then the device will return the ACK
and the master can then proceed with the next read or
write command. See Figure 5-1 for flow diagram.
The 24C08B/16B contains an address counter that
maintains the address of the last word accessed, inter-
nally incremented by one. Therefore, if the previous
access (either a read or write operation) was to
address n, the next current address read operation
would access data from address n + 1. Upon receipt of
FIGURE 5-1:
ACKNOWLEDGE POLLING
FLOW
the slave address with R/W bit set to one, the
24C08B/16B issues an acknowledge and transmits the
8-bit data word. The master will not acknowledge the
Send
Write Command
transfer but does generate a stop condition and the
24C08B/16B discontinues transmission (Figure 7-1).
7.2
Random Read
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, first the word address must
be set. This is done by sending the word address to the
24C08B/16B as part of a write operation. After the word
address is sent, the master generates a start condition
following the acknowledge. This terminates the write
operation, but not before the internal address pointer is
set. Then the master issues the control byte again but
with the R/W bit set to a one. The 24C08B/16B will then
issue an acknowledge and transmits the 8-bit data
word. The master will not acknowledge the transfer but
does generate a stop condition and the 24C08B/16B
discontinues transmission (Figure 7-2).
Did Device
Acknowledge
(ACK = 0)?
NO
7.3
Sequential Read
YES
Next
Operation
6.0 WRITE PROTECTION
The 24C08B/16B can be used as a serial ROM when
the WP pin is connected to V CC . Programming will be
inhibited and the entire memory will be write-protected.
Sequential reads are initiated in the same way as a ran-
dom read except that after the 24C08B/16B transmits
the first data byte, the master issues an acknowledge
as opposed to a stop condition in a random read. This
directs the 24C08B/16B to transmit the next sequen-
tially addressed 8 bit word (Figure 7-3).
To provide sequential reads the 24C08B/16B contains
an internal address pointer which is incremented by
one at the completion of each operation. This address
pointer allows the entire memory contents to be serially
read during one operation.
7.4
Noise Protection
The 24C08B/16B employs a V CC threshold detector
circuit which disables the internal erase/write logic if the
V CC is below 1.5 volts at nominal conditions.
The SCL and SDA inputs have Schmitt trigger and filter
circuits which suppress noise spikes to assure proper
device operation even on a noisy bus.
? 2004 Microchip Technology Inc.
DS21081G-page 7
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